1. Field of the Invention
Embodiments of the present invention generally relates to semiconductor processing technologies and, more specifically, to methods for fabricating a substrate containing dual damascene structures having low dielectric constant material thereon.
2. Description of the Related Art
Integrated circuits have evolved into complex devices that can include millions of components (e.g., transistors, capacitors and resistors) on a single chip. The demand for greater circuit density necessitates a reduction in the dimensions of the integrated circuit components, e.g., sub-micron dimensions and the use of various materials to fabricate devices in order to achieve much faster and better electrical performance, such as materials with higher conductivity used in metal lines, materials with lower permittivity (low-k) dielectric constant used as insulating materials, etc. For integrated circuit fabrication, metal interconnects with low resistance, such as copper and aluminum interconnects, provide conductive paths between the integrate circuit components on integrated circuit devices. Generally, metal interconnects are electrically isolated from each other by a dielectric bulk insulating material. At sub-micron dimensions, capacitive coupling potentially occurs between adjacent metal interconnects, which may cause cross talk and/or resistance-capacitance (RC) delay and degrade the overall performance of the integrated circuit.
Some integrated circuit components include multilevel interconnect structures, for example, dual damascene structures. Typically, dual damascene structures have dielectric bulk insulating layers and conductive metal layers, such as low dielectric constant materials and conductive copper layers, stacked on top of one another. Vias and/or trenches are etched into the dielectric bulk insulating layer and the conductive metal layers are subsequently filled into the vias and/or trenches and planarized, such as by a chemical mechanical planarization process (CMP), so that the conducting metal materials are only left in the vias and/or trenches. In the dual damascene approach, a rather complex dielectric stack that includes a sequence of hard mask, low-k dielectrics, and etch stop layers, etc., may be required. In addition, via lithography and patterning as well as trench lithography and patterning are required for fabricating the complex dielectric stack before filing the vias and the trenches with the conductive metal materials.
Different schemes to process a substrate containing dual damascene structures have been proposed. FIGS. 1A-1D illustrate an exemplary via-first scheme for processing vias and trenches in a dielectric stack 120. As shown in FIG. 1A, the dielectric stack 120 is formed over a substrate 100 having a dielectric layer 134 and a first layer of metal lines 140 formed thereon. The dielectric stack 120 includes from bottom to top a bottom barrier layer 130, a first dielectric bulk insulating layer 128, an optional middle etch stop layer 126, a second dielectric bulk insulating layer 124, and a top layer 122. The top layer 122 may be a capping layer, a hard mask layer, a dual hard mask layer, a etch stop layer, or a polish stop layer, suitable for protecting the underlying dielectric stack 120 during fabrication. The first and second dielectric bulk insulating layers 128, 124 are typically made of a low dielectric constant (e.g., κ lower than 4 material) for a copper dual damascene structure. The bottom barrier layer 130 can be silicon nitride, silicon carbide, silicon oxycarbide, or low k barrier materials. The top layer 122, and the middle etch stop layer 126 typically includes silicon oxy-nitride (SiON), tetra-ethyl-ortho-silicate (TEOS) based oxide, silicon carbide, silicon dioxide, silicon nitride, silicon oxycarbide, and the like.
In the via first scheme as shown in FIG. 1A, a via lithography process is performed first to form a first via mask 110 on top of the dielectric stack 120 and define via openings, such as an opening 101, for etching and patterning vias. As shown in FIG. 1B, etching is performed through the dielectric stack 120 and stopped at the bottom barrier layer 130 prior to stripping the via mask 110. In FIG. 1C, a trench lithography process is then performed to form a second trench mask 112 on top of the dielectric stack 120 to define trench openings, such as an opening 102, for etching and patterning trenches. Variation of the via first scheme may additionally include a bottom anti-reflective coating (BARC) layer to fill the opening 102 and cover the dielectric stack 120 before the trench lithography process. In a scheme of BARC processing, a hard mask layer may be additionally deposited over the BARC layer to serve as an etch mask layer in order to form trenches through lithography, patterning and BARC etching.
Referring back to FIG. 1D, once the trenches are formed by etching through the top layer 122 and the first dielectric bulk insulating layer 124, and stopped at the middle etch stop layer 126, if such layer is provided, or at the second dielectric bulk insulating layers 128, a via 111 and a trench 113 are finally formed and the trench mask 112 can be stripped away. As shown in FIG. 1D, the bottom barrier layer 130 is etched and opened up prior to filling the via 111 and trench 113 with a conductive metal material for forming electrical connections between the metal lines 140 and the conductive material of the via 111 and the trench 113.
A major problem arises when opening up the bottom barrier layer 130 and good etched profiles of the material stack can not be obtained, especially when the dielectric stack 120 containing porous low k materials. FIGS. 1E and 1F illustrate the structures of etching the bottom barrier layer 130 on the substrate containing a porous low k dielectric material stack 150. Even though good smooth etching profiles are obtained in the trench area of a substrate 100 after etching of the porous low k dielectric material stack 150, as shown in FIG. 2A; however, the results of etching the bottom barrier layer 130 performed on the same substrate 100, as shown in FIG. 2B, indicate that the corners 162 and the surfaces 161 of the substrate 100 are severely damaged. Since the bottoms of the trenches are exposed during etching of the bottom barrier layer 130, the exposed surface of the corners 162 are severely eroded away. In addition, for high aspect ratios structures, the surfaces 161 of the resulting bottom of the via 111 are often very rough, contaminated with etched residues and damaged structures. As a result, reliability of the fabricated device is severely affected.
In addition, as the devices dimensions decrease, especially at below 45 nm node and beyond, via critical dimension decreases dramatically as well, such that there are other iso-dense via micro-loading issues. As a results, selective etch chemistries and resist budget greatly increase the cost of device fabrication. A dual hard mask scheme has also been used, which require an etch chamber for etching a metal hard mask material and changing to a different chamber for etching most of dielectric materials; however, via micro-loading issues still exist. Besides, all of the above dual damascene fabrication schemes have problems to control the etch depths in the vias and trenches.
Therefore, there is a need for a method of uniformly fabricating a dual damascene structure to form a desired dimension and profile of material stacks.